Czasopismo | ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA | Rocznik 2012 - zeszyt 9

Features extraction system for automatic speech recognition core mapping into an irregular Network on Chip

nr katalogowy: 71008

As speech technologies become more and more prevalent they require efficient algorithms in its back end. This demand is required for fulfill speech processing time constrains since human speech communication is characterized by its dynamic behaviour. The most popular example of speech processing system is Automatic Speech Recognition (ASR). ASR system requires at least two modules to accomplish speech recognition in its basic form: feature extraction, extracting descriptor values for input speech data, and data classification [1]. The ASR processing is typically computational-intensive but it can be split into stages to be implemented in separate computational units. Thanks to this property they can benefit from parallel and distributed processing working in a pipeline-like way and transmitting each other streams of relatively large, but usually fixed, amount of data. In these applications, it is usually required to keep an assumed quality level of service and meet real-time constraints [10]. Multi Processor Systems on Chips (MPSoCs) are often considered as suitable hardware implementations of these applications [5]. As each processing unit of a MPSoC can realize a single stage of streaming application processing, it is still problematic to connect these units together. The simplest point to point (P2P) connections require too much space, whereas bus-based connections result in large number of conflicts and, consequently, despite various arbitrage techniques decrease the overall performance of the whole system [7]. Moreover, both P2P and bus-based realizations do not scale well with the constantly increasing number of independent Intellectual Property (IP) cores (i.e., computational units) required by contemporary devices dealing with a number of various algorithms in a single system [2]. In order to omit these obstacles, the packet-based Network-on-Chip (NoC) paradigm for designs of chips realizing distributed computation has[...]

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2012-9

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