Czasopismo | PRZEGLĄD ELEKTROTECHNICZNY | Rocznik 2021 - zeszyt 7

Design and Implementation of Parallel Multiplier Using Two Split Circuits

10.15199/48.2021.07.04

Salah Alkurwy

nr katalogowy: 132416
10.15199/48.2021.07.04

Streszczenie

A novel binary parallel multiplier circuit is designed and implemented in this study. The proposed multiplier is a combination of two split circuits, namely, truncated multiplier and least-significant bit (LSB) circuit. The LSB multiplier is designed based on the Vedic mathematic expression, but some modification is made for it to be compatible with the truncated multiplier and to achieve correct results for all the multiplication values. The designed circuit is coded by the Verilog hardware description language (HDL) using Quartus II. The register transfer level is verified, and the gate level is simulated using the Cyclone IV field programmable gate array (FPGA) platform. The proposed multiplier operates at 107.5 MHz frequency operating speed and requires 155 combinational logics. Comparison with other reported works shows that the proposed design has 19.5% less delay time. The new parallel multiplier is suitable for applications in various electronic devices due to its good feature

Abstract

W tym badaniu zaprojektowano i wdrożono nowatorski binarny równoległy obwód powielający. Proponowany mnożnik jest połączeniem dwóch oddzielnych obwodów, a mianowicie obwodu mnożnika obciętego i obwodu najmniej znaczącego bitu (LSB). Mnożnik LSB został zaprojektowany w oparciu o matematyczne wyrażenie wedyjskie, ale wprowadzono pewne modyfikacje, aby był zgodny z mnożnikiem obciętym i aby uzyskać poprawne wyniki dla wszystkich wartości mnożenia. Zaprojektowany obwód jest kodowany w języku opisu sprzętu Verilog (HDL) przy użyciu Quartus II. Poziom transferu rejestrów jest weryfikowany, a poziom bramki jest symulowany przy użyciu platformy programowalnej macierzy bramek (FPGA) Cyclone IV. Proponowany mnożnik działa przy częstotliwości roboczej 107,5 MHz i wymaga 155 logik kombinacyjnych. Porównanie z innymi zgłoszonymi pracami pokazuje, że proponowany projekt ma 19,5% krótszy czas opóźnienia. Nowy powielacz równoległy nadaje się do zastosowań w różnych urządzeniach elektronicznych ze

Słowa kluczowe

Keywords

Bibliografia

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