Czasopismo | ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA | Rocznik 2016 - zeszyt 9

The data retention control in NAND FLASH memory type

10.15199/13.2016.9.25

nr katalogowy: 101115
10.15199/13.2016.9.25

The data retention time is a very important parameter of NAND FLASH memory. The retention depends on the degradation level of memory cells parameters and it especially significantly depends on temperature. As an effect of the retention failures are the uncorrectable data errors and finally their loss. Because of it, data retention time should be checked and memory blocks with retention time shorter than specified should be excluded from further use. As indicated by studies, the test is burdened with some imperfections. An efficiency of data retention checking is limited, what is caused by memory construction and limited efficiency of control procedures, especially applying to a mass storage device. This article is focused entirely on data retention in NAND FLASH and on qualification errors. The diagnostic efficiency and the qualification errors were estimated by the use of computer simulation. Moreover, methods which allow reducing error value were proposed. Keywords: data retention, NAND FLASH, diagnostic, efficiency.The data retention is commonly observed in NAND FLASH memory. It is caused by a leakage of the electrical charge from the floating gate of memory cell transistor [3-6]. If the data retention time is shorter than specified, the one is treated as an error. In particular cases e.g. when NAND FLASH is planned to be used in a high temperature application, retention should be checked. That kind of control is performed in relevant production process, where solid state drives (SSD) and removable mass storage devices (MSD) are produced. In the control process, the thermal acceleration and the Arrhenius equation are commonly used in order to reduce retention time and to the extrapolation of normal time usage [6, 12-14]. Because the activation energy may depend on temperature, and the retention model may differ from the Arrhenius one [15, 16], the efficiency of those methods must be considered. Furthermore, Intel Inc. shows[...]

Bibliografia

[1] ONFI Workgroup, Open NAND Flash Interface Specification, ONFI Specification Rev. 3.0, ONFI Workgroup, March 2011, 49-53.
[2] Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, and Hiroshi Nakamura, (2002) Circuit Techniques for a 1.8-V-Only NAND Flash Memory, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 1, JANUARY 2002, 84-88.
[3] R. Micheloni, A. Marelli and S. Commodaro, (2010) Inside NAND FLASH Memories, Springer ISBN 978-90-481-9431-5, 19-52.
[4] Paolo Pavan, Roberto Bez, Piero Olivo, Enrico Zanoni, (1997) Flash Memory Cells—An Overview, IEEE TRANSACTIONS ON RELIABILITY, VOL. 85, NO. 8, AUGUST.
[5] Praca zbiorowa, Changes in Non Volatile Memory Qualification Methods, Intel Corporation, Santa Clara, CA, USA
[6] Committees:JC-14.3, JC-14, Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Stress Test, JEDEC STANDARD JESD22-A117C, JEDEC Solid State Technology Association, Arlington USA, OCTOBER 2011.
[7] Committees: JC-14.1, JC-14, Failure Mechanisms and Models for Semiconductor Devices, JEDEC PUBLICATION JEP122G, JEDEC Solid State Technology Association, Arlington USA, OCTOBER 2011, 9, 22-27, 76-80.
[8] Yasuhiko Honda, Hiratsuka-shi, (2013) NAND FLASH Memory, United States Patent Application Publication, US 2011/0128788 A1, Jun. 2.
[9] Open NAND Flash Interface Specification, Revision 4.0 04-02-2014, www.onfi.org
[10] Krzysztof Bąk, (2013) Projektowanie testu aplikacyjnego układów pamięci NAND FLASH, Biuletyn WAT Vol. LXII , Nr 4.
[11] Silicon Motion Inc., SM2244LT Product Brief,
[12] Toshiba, Reliability Testing - chapter 3, www.toshiba.com
[13] Committee: JC-14.1, High Temperature Storage Life, JEDEC PUBLICATION JESD22-A103D, November 2004, www.jedec.org
[14] Kripasagar Venkat, Uwe Haensel, (2008) Understanding MSP430 Flash Data Retention, doc. SLAA392, Texas Instruments.
[15] Steven Hetzler, (2014) Flash Temperature Testing And Modeling, Flash Memory Summit.
[16] Praca zbiorowa, (2013) Analysis of Temperature Dependence and the Apparent Activation Energy (Ea) on PV state of Sub 20-nm NAND Flash Memory, ISDRS 2013, December 11-13.
[17] Bąk K., Badura D., (2015), Symulacja uszkodzeń pamięci typu NAND FLASH, Wydawnictwo Wyższej Szkoły Biznesu w Dąbrowie Górniczej, s. 103-134.
[18] Władysław Mochnacki, (2000) Kody Korekcyjne i Kryptografia, Oficyna Wydawnicza Politechniki Wrocławskiej, Wrocław .
[19] Yu Cai, Onur Mutlu, Erich F. Haratsch, Ken Mai, (2013) Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation, IEEE 31st International Conference on Computer Design (ICCD), e-ISBN: 978-1-4799-2987-0, 123-130.
[20] Praca zbiorowa, (2010) A 159 mm2 32nm 32Gb MLC NANDFlash Memory with 200MB/s Asynchronous DDR Interface, IEEE International, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), ISBN: 978-1-4244-6033-5, 442-443.
[21] Praca zbiorowa, (1996) A 117-mm 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, IEEE Journal of Solid-State Circuits (Volume:31 , Issue: 11 ), ISSN: 0018-9200.
[22] Douglas Sheldon, Michael Freie, Disturb Testing in Flash Memories, California Institute of Technology Pasadena, California / Semiconductor Solutions, Inc. Sparks, Nevada, JPL Publication 08-7 3/08.
[23] Seiichi Aritome, Riichiro Shirota, Gertjan Hemink, Tetsuo Endoh, and Fuji Masuoka, (1993) Reliability Issues of Flash Memory Cells, IEEE, PROCEEDINGS OF THE IEEE. VOL. 81. NO. 5, ISSN: 0018-9219, 776 - 788.
[24] Anthony K. Akobeng, (2006) Understanding diagnostic tests 1: sensitivity, specificity and predictive values, Acta Paediatrica, ISSN: 0803-5253.
[25] Roman Jaeschke, Deborah Cook, Gordon Guyatt, (2001) Metody określania przydatności testu, Departament Medycyny Wewnętrznej i Departamentu Epidemiologii Klinicznej i Biostatystyki, McMaster University, Hamilton, Kanada
[26] American National Standard, ATA/ATAPI Command Set - 2 (ACS-2), American National Standard dok. T13/2015-D, Revision 1a March 2, 2009, www.t13.org

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