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Pros and cons of system-level synthesis of data-dominated algorithms

  In case of multi-core systems, it is practically impossible to simulate them at low levels of abstraction, owing to its long time that postpones time-to-market (TTM) for a considered product. For example, simulating a boot-up sequence of a mobile phone at a register-transfer level (where entities are registers, latches, multiplexers, etc.), takes more than six months, whereas the same simulation carried out on a higher, system level model level (where each entity resembles program language objects whose communicate each other executing appropriate functions), takes about one week (Information obtained during a private talk with an employee from one of a world top mobile phone producers). But the possibilities of efficient synthesis directly from this level, without rewriting the models into a lower level of abstractions is still an open questions. According to the authors knowledge, despite numerous appeals, nobody published a widely accepted set of benchmarks for system-level synthesis. Taking into account the progress in logic design after publishing the ISCAS85 set or ITC’99 set often used at higher level of digital design, one may draw the conclusion that this lack of popular benchmarks hampers the progress in design at this level and makes the comparison between results of various group of scientists almost impossible. Similarly, despite a few reports (e.g. [4] or [8]), in order to compare the hardware synthesis performed from system and architectural level of abstraction, one has rather to perform one’s own observations as there is still, according to the literature study of the authors, no comparison between these numbers for a wide set of popular functions. Besides, some brochures or tutorials of EDA companies (such as [7]) show even that the design from the system level leads to better results than synthesis from lower abstraction levels, that is intuitively possible for a rather narrow classes of probl[...]

Formal analysis of destination reachability under given restrictions for multi-path routing in Network on Chip

  Networks on Chips (NoCs) have proved their assets as a mean of communication for future Multi-Processor Systems on Chips (MPSoCs) [2]. The majority of research in this field, however, assumes the mesh NoCs and a single-path wormhole switching utilizing the XY routing algorithm [3]. This assumptions deteriorates the potential of NoCs. As we checked in our earlier work [6], for typical multimedia algorithms the NoCs’ links are far from being utilized in a balanced way. Similarly, using the state-of-the-art XY routing algorithm, a number of links is not utilized at all while others are characterized with a large number of contentions. Thus the relatively large portion of links in a mesh can be omitted without any influence on the total transfer or latency of the NoC. It is not necessary to have a number of paths between two nodes if, due to the XY routing algorithm, only one of them can be utilized. This is in sheer contrast with the traditional computer networks, where multi-path routings are omnipresent. This fact can be explained with the difference in router requirements between these two networks scales. In NoCs the implementation cost of mechanisms needed for streams splitting and joining is significant both in terms of time and chip area. The benefits of higher utilization of links and improved balance is often lost by the additional spatial and/or temporal requirements [10]. The situation may look a bit different in case of the typical multimedia data processing system, which are usually computation- intensive and utterly dominated by data. MPSoCs realizing these algorithms are characterized with a relatively large amount of data transmitted between cores, what requires the guarantee of sufficient bandwidth of the connections to work in real-time. As a transfer pattern is the same during relative long time, i.e., during executing the same application in NoC, contentions are especially likely to occur, as it was show[...]

Stream-based cores mapping strategies dedicated to Networks on Chip architecture

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The Multi Processor Systems on Chips (MPSoCs) are often considered as being suitable for streaming multimedia applications [5]. However, contemporary bus-based MPSoCs do not scale enough to maintain the foreseen growth of the number of intellectual property (IP) cores in a single chip [2]. It is one of the reasons of the ubiquitness of the packet-based Network-on-Chip (NoC) architectures in [...]

Network-on-Chip-based realization of a lossless compression system

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It is widely known that according to The International Technology Roadmap for Semiconductors [14], System on Chips (SoCs) will grow up to 4 billion transistors running at 10 GHz by the end of the decade. One of the major concerns addressed in that report is connected with scaling of global interconnect performance relative to device performance. This communication infrastructure will be conn[...]

System-level model of hardware assisted still image compression based on two dimensional principal component analysis

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There are many storage formats for digital images in the PC environment, however hardly no one meets their specific nature. One of the most popular - JPEG/JFIF [13] - is a compromising solution: it gives high compression ratios while retaining acceptable visual quality [13]; its encoders and practical implementations are efficient and easy to use. On the other hand, JPEG has many limitations[...]

System-level perspective of computation and communication refinement for a subpredictor-blending-based compression system

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The Electronic System Level (ESL) design is a more and more popular approach for designing System on Chips (SoCs), that is used as an established methodology in the majority of the world largest SoC design companies for concurrent design of hardware and software [1]. Despite its popularity, the definition of ESL is still not yet established. Typically, engineers working in the domain agree t[...]

Multi-core realization of audio decoders utilizing on-chip networks

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The Multi-Processor Systems on Chips (MPSoCs) are viewed as suitable for future generation of streaming multimedia applications [1]. As modern bus-based and point-to-point (P2P) MPSoCs do not scale enough to maintain the foreseen growth of the number of intellectual property (IP) cores in a single chip [5], the packet-based Network-on-Chip (NoC) architectures are perceived as the necessity o[...]

A system-level model of a FLAC codec

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Digital sound recording in the uncompressed way requires enormous memory resource. For example, a file with 3-minute stereo signal with the sampling frequency 44 100 Hz and 16 bits per sample requires about 30 MB. The main features of the compression techniques of audio signal are [3]: (i) they can be lossy due to the imperfection of human audio perception, and (ii) they require fast decoding to be played without delay in real-time. One of the most popular lossy codec is MPEG-1 Audio Layer 3, often abbreviated as MP3. The lossless audio codecs are of lower popularity, but they are anyway needed for a various applications. One of the most popular lossless audio codec is FLAC (Free Lossless Audio Codec) [1]. It is based on the approximation of the subsequent audio samples using [...]

Adaptive tree-based multicast routing in network on chip architecture

  Modern high-end digital systems require processing between many heterogeneous functional units. Their demands for efficient on-chip communication become greater as the number of systems functional units grows. The performance of such systems is mainly limited by their communication capabilities [5]. The new requirements like need for handling mixed types of traffic, quality of service assurance and even need for sharing resources caused that the traditional bus-based system architectures became no longer suitable for such systems. The integrated circuits evolve, components become smaller, faster and more powerful, but their complexity grows as well. While the processing technology is developing at a rather fast pace, the communication technology remains almost unchanged, which leads to increasing the unbalance between gate delays and wire delays on chip [3]. Contemporary high-end systems most of the power use to drive wires and most of the clock cycle is spent on wire delay, not gate delay [5]. The main motivation for using on-chip networking is to achieve better performance. The advantage of NoC is that only point-to-point one-way wires are used, for all network sizes, thus local performance is not degraded when scaling, in contrast to buses where every unit attached adds parasitic capacitance, therefore electrical performance degrades with growth [1,3]. Efficient multicast communication when considering scalable multiprocessor architectures plays very important role. The message routing algorithm determines the overall system performance. Since the support for on-chip multicast in current multiprocessors is very poor (mostly multicast is implemented as set of multiple unicast messages [10]) the demand for high effective, low latency algorithms is even greater. Despite the fact that there are number of multicast algorithms for off-chip area, they cannot be straightway applied for on-chip domain because of the tight constra[...]

Path-based multicast routing in network on chip architecture

  Application of many heterogeneous functional units are of mounting popularity in the current top-end digital systems. However, the performance of a system’s functional unit is limited due to the delays of the communication between them [5]. What is even worse, the need for such intense communication increases as the systems become larger. The architecture of a conventional bus-based system becomes obsolete due to the quality assurance, handling mixed traffic and resource sharing requirements. The computational units become smaller, much more powerful and faster. Unfortunately, a gap has been created between processing technology and communication technology which leads to increasing the unbalance between gate delays and wire delays [3]. Contemporary highend systems most of the power use to drive wires and most of the clock cycle is spent on wire delay, not gate delay [6]. On-chip networking has been introduced in order to tackle these communication problems. However, a typical Network on Chip (NoC) uses one-way wires which run from point A to point B, rather than using buses connected to a number of destination cores. This makes sending of a single package to a number of destination nodes (i.e., multicast traffic) more difficult [1, 3]. Although there are many multicast algorithms for the traditional TCP/IP networks, they cannot be applied immediately to the NoC field due to the stringent restrictions imposed by this architecture. Also multicast support in a modern multiprocessors is currently very poor, as usually multicast is implemented as multiple unicast communication [12]. There is still need of competent multicast communication and the application of high efficiency, yet low latency, multicast algorithms [5]. Keeping that in mind, we developed an adaptive algorithm for multicast communication in NoCs. In general, NoCs use three different groups of components. These are cores, interconnection channels and router[...]

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